India’s chip design challenge is moving from IP to commercialisation: Cadence

India’s semiconductor industry is entering a phase where creating chip designs and intellectual property is no longer the only challenge. The next hurdle is turning those designs into products that can reach scale and compete on cost with established global players, according to Jayashankar Narayanankutty, Group Director at Cadence Design Systems.

“When the Semicon policy was announced late in 2021, the industry expectation was the DLI amount today will probably have about 30 companies. I think the biggest and the most pleasant surprise is the number of companies that have actually come out,” Narayanankutty told Fortune India. 

“About 105 companies have been supported through the DLI. About 24 of them have actually been supported with financial support. And 20 of them have raised close to hundred million dollars,” he said.

The government has said 24 semiconductor design projects have been approved for financial support under the Design Linked Incentive (DLI) scheme, while 105 startups and MSMEs have been given access to electronic design automation tools. The government has also reported 23 chip tape-outs under the scheme.

“So I think the biggest takeaway in the last five years is purely the validation of the strategy that the government employed in being able to build the ecosystem, and the reaction from the industry saying that, okay, it’s time for us to have Indian IP in India, or India for India,” Narayanankutty said.

India’s chip startups face a commercialisation gap

The next challenge, however, is moving from design to product. “I think [it is] fundamentally going from a design phase to a product phase. And I’m not speaking about manufacturing,” Narayanankutty said.

Putting up a factory or getting a chip manufactured is only one part of the process, he said. The bigger challenge is getting the finished product to customers at a price that makes commercial sense. “But beyond that, it has to be made available to a customer at a cost that makes sense for the customer. And there is a big gap there,” he said. 

Indian chip companies could find themselves competing against global players that have already recovered their development and manufacturing costs, making it difficult for newer companies to match their pricing. “In some of the cases where our customers are competing, there are worldwide players who have fully depreciated processes, who are able to provide price points that obviously we are not in,” Narayanankutty said.

He described this as a value gap that India will need to address if its semiconductor companies are to become globally competitive.

One approach could be to create demand for indigenous silicon in specific markets. “What we are doing with security and surveillance, we’re saying that everything has to be indigenous silicon, or native silicon,” he said. Another approach could be financial support to help companies bridge the gap until they achieve sufficient scale.

For Indian chip companies, this creates a chicken-and-egg problem--they need scale to become competitive, while competitiveness is needed to achieve scale. “As we understand that for us to become competitive, we have to get to volume. And for us to get to volume, we have to be competitive,” he said; suggesting that actions need to be taken by industry and the government. 

AI can accelerate chip design, but not replace engineers

Artificial intelligence is also changing how semiconductor design is carried out. Cadence has been developing AI-based tools and agents that can automate parts of the design process, while keeping engineers involved in the workflow. Narayanankutty said Cadence has been working on AI and optimisation for more than a decade, with the latest generation of AI agents building on that work. “We have been thinking about artificial intelligence for more than a decade now. Every optimisation that we did in the past is in a form of artificial intelligence,” he said.

He described Cadence’s approach as a three-layer system involving agents that orchestrate tasks, algorithms that perform the underlying work, and dedicated hardware that runs those algorithms. The biggest change, he said, could be the ability to identify problems earlier in the design cycle. “The agent is not only looking at the first-order problem which you’re solving for, it is also looking at the end-order problem, which is downstream and you have not gotten to,” Narayanankutty said. “And therefore, it is a shift left. What the problem that you would have met with day after tomorrow, you know it’s coming today.”

That could allow engineers to spend less time on repetitive work and more time running experiments as chip designs become increasingly complex. “The human in the loop gets accelerated,” he said.

However, Narayanankutty does not expect AI to completely automate chip design. “I’m old school where I’ve been doing this for 32 years now, and I’m going to emphatically say no,” he said when asked whether chip design could eventually become fully automated. “Chip design is a very complicated endeavour. You’re dealing with geometries that are at the edge of our imagination.”

As designs become smaller and more complex, he said, the relationship between inputs and outputs becomes increasingly difficult to predict. “And in a non-deterministic world, you can’t automate for everything. You can only automate for specific things,” he said. “I don’t foresee you push a button and the chip comes out; [that's] not happening.”